The invention is generally related to the field of MOSFET transistors and more specifically to a novel process to reduce the junction depth of the source and drain extension regions.
Shown in FIG. 1 is a cross-sectional diagram of a typical metal oxide semiconductor (MOS) transistor 5. The MOS transistor 5 is fabricated in a semiconductor substrate 10. The MOS transistor comprises a gate dielectric layer 20 that is formed on the surface of the substrate 10. Typically this gate dielectric layer is formed using silicon oxide or nitrided silicon oxide although many other materials such as silicates have been used. The MOS transistor gate structure 30 is formed on the gate dielectric layer 20 land is typically formed using polycrystalline silicon. In addition to polycrystalline silicon other materials such as metals have been used to form the transistor gate. The combined dielectric layer/gate structure is often referred to as the gate stack. Following the formation of the transistor gate stack the source-drain extension regions 40 are formed using ion implantation. In forming these extension regions 40 dopants are implanted into the ""substrate using the gate stack as a mask. Therefore the extension regions 40 are aligned to the gate stack in what is known as the self-aligned process. Following the formation of the extension regions 40, sidewall structures 50 are formed adjacent to the gate stack. These sidewall structures 50 are typically formed by depositing one or more conformal films on the surface of the substrate followed by an anisotropic etch process. This anisotropic etch will remove the conformal film[s] from all regions of the surface except those adjacent to gate stack structures. This results in the sidewall structures 50 shown in FIG. 1. Following the formation of the sidewall structures the source and drain regions 60 are formed using ion implantation. The structure is then annealed at a high temperature to activate the implanted dopant species in both the extension regions 40 and the source and drain regions 60. During this high temperature anneal the dopants will diffuse into the semiconductor substrate. This dopant diffusion will result in a final junction depth of xj for the extension regions 40.
As MOS transistor dimensions are reduced there is a need to reduce the junction depth xj of the extension regions 40. Typically this is accomplished by reducing the implantation dose and energy of the dopant species used to form the extension regions 40. This often leads to an increase in the drain land source resistance of the MOS transistor resulting in a degrading of the MOS transistor performance. There is therefore a need to reduce the extension junction depth xj without degrading MOS transistor performance.
The instant invention describes a method for forming thermal CVD oxynitride and BTBAS nitride sidewall spacers during MOS transistor fabrication. In particular a gate stack is formed on a semiconductor substrate. An optional offset spacer is formed adjacent to the gate stack before the formation of extension regions. The sidewall structure is formed using silicon oxynitride layers and silicon nitride layers formed over the gate stack and the silicon substrate. The atomic nitrogen concentration in the silicon oxynitride layer is between 2 to 15 atomic percent. In a further embodiment of the instant invention the sidewall structures will comprise alternating layers of silicon oxide and silicon nitride.
Technical advantages of the instant invention include a reduction in the boron diffusion obtained during thermal annealing cycles. Other technical advantages will be readily apparent to one skilled in the art from the following figures, description, and claims.